1. Field of the Invention
The present invention relates to a multiplexor, and more specifically to a multiplexor composed of dynamic latches.
2. Description of Related Art
A prior art multiplexor will be described with reference to an example of a 2-bit multiplexor, since a multi-bit multiplexor can be constituted by combining 2-bit multiplexors. This is well known, as already described by, for example, K. Ishida et al, "A 10-GHz 8-b Multiplexor/Demultiplexor Chip Set for the SONET STS-192 System", IEEE Journal of Solid-State Circuits, Vol.26, No.12, December 1991, pages 1936-1943, and C. L. Stout et al., "10-Gb/s Silicon Bipolar 8:1 Multiplexor and 1:8 Demultiplexor", IEEE Journal of Solid-State Circuits, Vol.28, No.3, March 1993, pages 339-343. The content of these papers are incorporated by reference in its entirety into this application.
Referring to FIG. 23, there is shown a block diagram of the basic construction for illustrating an operation principle of the prior art 2-bit multiplexor. As shown in FIG. 23, the shown 2-bit multiplexor includes a latch L1 having a data input D1 connected to a first data input terminal IN1, a non-inverted clock input C1 connected to a non-inverted clock input terminal CLK, an inverted clock input C1B connected to an inverted clock input terminal CLKB, and an output Q1 connected to a node 01, a latch L2 having a data input D2 connected to a second data input terminal IN2, a non-inverted clock input C2 connected to the non-inverted clock input terminal CLK, an inverted clock input C2B connected to the inverted clock input terminal CLKB, and an output Q2 connected to a node 02, a latch L3 having a data input D3 connected to the node 02, a non-inverted clock input C3 connected to the inverted clock input terminal CLKB, an inverted clock input C3B connected to the non-inverted clock input terminal CLK, and an output Q3 connected to a node 03, and a selector S having a first input A connected to the node 01, a second input B connected to the node 03, a non-inverted selection signal input S connected to the non-inverted clock input terminal CLK, an inverted selection signal input SB connected to the inverted clock input terminal CLKB, and an output connected to an output terminal OUT.
Now, an operation of the circuit shown in FIG. 23 will be described with reference to a timing chart shown in FIG. 24. Since an inverted signal of a signal applied to the non-inverted clock input terminal CLK is applied to the inverted clock input terminal CLKB, only the non-inverted clock input terminal CLK is shown in FIG. 24 and will be described in the following description.
When a low level signal is applied to the non-inverted clock input terminal CLK, the latch L1 and the latch L2 fetch the data, so that the fetched data is outputted from the output Q1 and Q2, and on the other hand, the output Q3 of the latch L3 holds the preceding data. When the signal applied to the non-inverted clock input terminal CLK is brought to a high level, the outputs Q1 and Q2 of the latches L1 and L2 hold the data fetched when the signal applied to the non-inverted clock input terminal CLK is at the low level. On the other hand, the latch L3 fetches the data outputted from the latch L2, so that the newly fetched data is outputted from the output Q3 of the latch L3.
As shown in FIG. 24, the output Q1 of the first latch L1 and the output Q3 of the third latch L3 are shifted in phase from each other by a half period of the clock, and are supplied to the inputs A and B of the selector S. The selector S outputs the value of the input A when the signal applied to the non-inverted clock input terminal CLK is at the high level, and the value of the input B when the signal applied to the non-inverted clock input terminal CLK is at the low level.
Referring to FIG. 25, there is shown a circuit diagram of an example of the prior art multiplexor which is constituted of the least number of circuit elements and includes the least number of transistors driven with control signals. In the circuit shown in FIG. 25, the latch L1 of FIG. 23 constituted of a transfer gate TG1 and an inverter INV1, the latch L2 of FIG. 23 constituted of a transfer gate TG2 and an inverter INV2, the latch L3 of FIG. 23 constituted of a transfer gate TG3 and an inverter INV3, and the selector S of FIG. 23 is constituted of two transfer gates TG4 and TG5.
Now, an operation of the shown in FIG. 25 will be described. When the signal applied to the non-inverted clock input terminal CLK is at the low level, the transfer gates TG1, TG2 and TG5 are opened and the transfer gate TG3 and TG4 are closed, so that nodes 101 and 103 are charged or discharged in accordance with the value of the data input terminals IN1 and IN2, respectively. As a result, an inverted value of the data input terminal IN1 is outputted to a node 102, and an inverted value of the data input terminal IN2 is outputted to a node 104, and on the other hand, an inverted value of a dynamic node 105 is outputted to the output terminal OUT. When the signal applied to the non-inverted clock input terminal CLK is brought to the high level, the transfer gates TG1, TG2 and TG5 are closed and the transfer gate TG3 and TG4 are opened, so that the inverted value of the data input terminal IN1 is outputted to the output terminal OUT.
The circuit shown in FIG. 25 is one of the circuits which are constituted of the least number of circuit elements and include the least number of transistors driven with control signals, in multiplexors composed of MOS transistors and having its amplitude fully swinging between a pair of power supply voltages. However, since the clock signals are used for controlling the latches and the selector, a large electric power is consumed for driving the latches and the selector. In addition, if a multi-bit multiplexor is constituted of 2-bit multiplexors, the electric power consumption becomes further large.